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File:Coreboot logo.svg
Original author(s) Ronald G. Minnich, Eric Biederman, Olli Lo, Stefan Reinauer, the coreboot community
Initial release 1999
Stable release 2
Preview release 3
Platform x86, PPC
Type Firmware
License GNU General Public License

Coreboot (formerly known as LinuxBIOS[1]) is a free software project, endorsed by the Free Software Foundation,[2] aimed at replacing the proprietary BIOS firmware found in most computers with a lightweight system designed to perform only the minimum of tasks necessary to load and run a modern 32-bit or 64-bit operating system.

The coreboot project was started in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory.[3] It is licensed under the terms of the GNU General Public License. Main contributors have been LANL, AMD, coresystems GmbH and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte and Tyan, by offering coreboot next to their standard BIOS or providing specifications of the hardware interfaces for some of their recent motherboards. However, Tyan seems to have dropped support of coreboot.[citation needed] Google partly sponsors the coreboot project.[4] CME Group, a cluster of futures exchanges, began supporting the coreboot project in 2009.[5]

Coreboot support also exists for the AMD Geode. Started as Geode GX support developed by AMD for the OLPC, Artec Group then added Geode LX support for its model DBE61 ThinCan. Recently, that code was adopted by AMD and further polished for the OLPC after it upgraded to the Geode LX platform. That code is now being further developed by the coreboot community to support other Geode-based products.

Coreboot can be flashed into a motherboard using Flashrom.



Coreboot usually loads a Linux kernel, but it can load any other stand-alone ELF executable, such as Etherboot which can boot Linux from a boot server or SeaBIOS[6] which loads Microsoft Windows 2000/XP/Vista/7 and *BSD (previously, Windows 2000/XP and OpenBSD support was provided by ADLO[7][8]). Coreboot can also load almost any operating system from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Some OSes require legacy BIOS functions (such as Windows 2000/XP/Vista/7 and *BSD) which are provided by SeaBIOS.

A unique feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions[9] (almost all other x86 BIOSes run exclusively in 16-bit mode).

Coreboot can boot other kernels, or pass control to a boot loader to boot a kernel/image instead. It can also boot a Plan 9 from Bell Labs kernel directly. A coreboot capable version of GNU GRUB 2 is still in development.

By default, coreboot does not provide BIOS call services. A payload called SeaBIOS can be used to provide BIOS calls and thus allow coreboot to load operating systems that require those services, however most modern operating systems access hardware in another manner and only use BIOS calls during early initialization and as a fallback mechanism.

Developing and debugging coreboot

Since coreboot must initialize the bare hardware, it must be ported to every chipset and motherboard that it supports. Before initializing RAM, coreboot initializes the serial port (addressing cache and registers only), so it can send out debug text to a connected terminal. It can also send byte codes to port 0x80 that are displayed on a two-hex-digit display of a connected POST card. Another porting aid is the commercial "RD1 BIOS Savior" product from IOSS[10], which is a combination of two boot memory devices that plugs into the boot memory socket and has a manual switch to select between the two devices. The computer can boot from one device, and then the switch can be toggled to allow the computer to reprogram or "flash" the second device. A more expensive alternative is an external EPROM/flash programmer. There are also CPU emulators that either replace the CPU or connect via a JTAG port. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.


Coreboot can load a payload.

  • Etherboot can boot an operating system over the network. gPXE which is the successor to Etherboot works when run under SeaBIOS.
  • SeaBIOS is an implementation of x86 BIOS.

Initializing DRAM

The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA protected or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache-as-RAM as temporary storage. To ease this hard task, romcc was built. It is a C compiler that uses registers instead of RAM. Using romcc, it is relatively easy to make SMBus accesses to the SPD ROMs of the DRAM DIMMs, that allows the RAM to be used. With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM[11] mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is CPU architecture specific, thus more generic than DRAM initialization, which is chipset and mainboard specific.

See also


Further reading

External links

es:Coreboot fr:Coreboot hr:Coreboot it:Coreboot pl:Coreboot pt:Coreboot ru:Coreboot sv:Coreboot

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