VHDL

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VHDL
Paradigm concurrent, reactive
Appeared in 1980s
Typing discipline strong
Influenced by Ada, Pascal
Website IEEE VASG
File:Vhdl signed adder.png
VHDL source for a signed adder.

VHDL (VHSIC hardware description language; VHSIC: very-high-speed integrated circuit) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

Contents

History

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest area, lowest power consumption, highest clock speed, or other requirements.

VHDL borrows heavily from the Ada programming language in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly typed and is not case sensitive. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to directly represent operations which are common in hardware. VHDL also allows arrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the Department of Defense required as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada.

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector.

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions.

In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was approved by REVCOM in September 2008.

Design

VHDL is a fairly general-purpose language, and it doesn't require a simulator on which to run the code. There are many VHDL compilers, which build executable binaries. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements.

VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software (such as ModelSim) which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.

The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behavior, working together at the same time). VHDL is a Dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time.

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

Getting started

Although background in a computer programming language (such as C and C++) is helpful, it is not essential. Free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user's goal is to learn RTL coding, (that is, design hardware circuits in VHDL, as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also needed.

As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.

Nearly all FPGA design and simulation flows support both VHDL and Verilog, another hardware description language, allowing the user to learn either or both languages.

Free design & simulation packages for VHDL/Verilog:

Vendor Trial Software License Simulator Synthesizer RTL view Gate view
Actel Libero gold one year free license ModelSim Actel Edition Synplify Actel Edition No Yes**
Aldec Active-HDL (Student Edition) one year free license Aldec (mixed language) Student All Synthesis (interfaces) Yes Yes
Altera Quartus II web edition no license needed ModelSim Altera Edition Altera Quartus II Yes Yes**
Blue Pacific BlueHDL free license BlueSim ? ? ?
Dolphin none free Seduction license [1] SMASH No ? ?
GHDL GHDL GPL GHDL No via GTKWave No
Lattice ispLEVER Starter 6 months renewable free license Aldec Active-HDL Lattice Web Edition Synopsys Synplify Lattice Edition No Yes
Mentor Graphics none 6 months renewable free license ModelSim PE Student Edition No Yes No
Symphony EDA VHDL Simili Free license[2] Sonata Sonata Yes No
Xilinx ISE webpack free license ISE Simulator* Xilinx XST Yes Yes**

* If Modelsim is installed on the computer, the ISE software can call ModelSim's features if desired. (ISE 9.2i comes with an integrated simulator)
** Limited to vendor's device-database

Code examples

In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations.

A simple AND gate in VHDL would look something like this:

-- (this is a VHDL comment)
 
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
 
-- this is the entity
entity ANDGATE is
   port ( 
         IN1 : in std_logic;
         IN2 : in std_logic;
         OUT1: out std_logic);
end ANDGATE;
 
architecture RTL of ANDGATE is
begin
 
  OUT1 <= IN1 and IN2;
 
end RTL;

While the example above may seem very verbose to HDL beginners, one should keep in mind that many parts are either optional or need to be written only once. And generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

In the examples that follow, you will see that VHDL code can be written in a very compact form. However, the experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability. Another advantage to the verbose coding style is the smaller amount of resources used when programming to a Programmable Logic Device such as a CPLD[citation needed].

Synthesizeable constructs and VHDL templates

VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC. Many FPGA vendors have free (or inexpensive) tools to synthesize VHDL for use with their chips, where ASIC tools are often very expensive.

Not all constructs in VHDL are suitable for synthesis. For example, most constructs that explicitly deal with timing such as wait for 10 ns; are not synthesizable despite being valid for simulation. While different synthesis tools have different capabilities, there exists a common synthesizable subset of VHDL that defines what language constructs and idioms map into common hardware for many synthesis tools. IEEE 1076.6 defines a subset of the language that is considered the official synthesis subset. It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs.

Some examples of code that map into hardware multiplexers in common tools follow:

MUX templates

The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs A and B, selector S and output X:

 
-- template 1:
X <= A when S = '1' else B;
 
-- template 2:
with S select
  X <= A when '1',
       B when others;
 
-- template 3:
process(A,B,S)
begin
  case S is
    when '1'    => X <= A;
    when others => X <= B;
  end case;
end process;
 
-- template 4:
process(A,B,S)
begin
  if S = '1' then
    X <= A;
  else
    X <= B;
  end if;
end process;
 
-- template 5 - 4:1 MUX, where S is a 2-bit std_logic_vector :
process(A,B,C,D,S)
begin
  case S is
    when "00"   => X <= A;
    when "01"   => X <= B;
    when "10"   => X <= C;
    when others => X <= D; 
  end case;
end process;

The three last templates make use of what VHDL calls 'sequential' code. The sequential sections are always placed inside a process and have a slightly different syntax which may resemble more traditional programming languages.

Latch templates

A transparent latch is basically one bit of memory which is updated when an enable signal is raised:

-- latch template 1:
Q <= D when Enable = '1' else Q;
 
-- latch template 2:
process(D,Enable)
begin
  if Enable = '1' then
    Q <= D;
  end if;
end process;

A SR-latch uses a set and reset signal instead:

-- SR-latch template 1:
Q <= '1' when S = '1' else
  '0' when R = '1' else Q;
 
-- SR-latch template 2:
process(S,R)
begin
  if S = '1' then
    Q <= '1';
  elsif R = '1' then
    Q <= '0';
  end if;
end process;

Template 2 has an implicit "else Q <= Q;" which may be explicitly added if desired.

-- This one is a RS-latch (i.e. reset dominates)
process(S,R)
begin
  if R = '1' then
    Q <= '0';
  elsif S = '1' then
    Q <= '1';
  end if;
end process;

D-type flip-flops

The D-type flip-flop samples an incoming signal at the rising or falling edge of a clock. The DFF is the basis for all synchronous logic.

-- simplest DFF template (not recommended)
Q <= D when rising_edge(CLK);
 
-- recommended DFF template:
process(CLK)
begin
  -- use falling_edge(CLK) to sample at the falling edge instead
  if rising_edge(CLK) then
    Q <= D;
  end if;
end process;
 
-- alternative DFF template:
process
begin
  wait until CLK='1';
  Q <= D;  
end process;
 
-- alternative template expands the ''rising_edge'' function above:
process(CLK)
begin
   if CLK = '1' and CLK'event then--use rising edge, use  "if CLK = '0' and CLK'event" instead for falling edge
      Q <= D;
   end if;
end process;

Some flip-flops also have Enable signals and asynchronous or synchronous Set and Reset signals:

-- template for asynchronous reset with clock enable:
process(CLK, RESET)
begin
  if RESET = '1' then   -- or '0' if RESET is active low...
    Q <= '0';
  elsif rising_edge(CLK) then
    if Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;
 
-- template for synchronous reset with clock enable:
process(CLK)
begin
  if rising_edge(CLK) then
    if RESET = '1' then 
      Q <= '0';
    elsif Enable = '1' then  -- or '0' if Enable is active low...
      Q <= D;
    end if;
  end if;
end process;

A common beginner mistake is to have a set or reset input but not use it. For example, the following two snippets are not equal, the first one is a simple D-type flip-flop, while the second one is a DFF with a feedback MUX.

-- simple D-type flip-flop 
process(CLK)
begin
  if rising_edge(CLK) then  
    Q <= D;  
  end if;
end process;
 
-- BAD VHDL: this does NOT make the flip-flop a DFF without a reset!!
process(CLK, RESET)
begin
  if RESET = '1' then  
  	-- do nothing. Q is not set here...  
  elsif rising_edge(CLK) then  
    Q <= D;  
  end if;
end process;

This is very similar to the 'transparent latch' mistake mentioned earlier.

Example: a counter

The following example is an up-counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type and VHDL generics. The generics are very close to arguments or templates in other traditional programming languages like C or C++.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type
 
entity counter_example is
generic ( WIDTH : integer := 32);
port (
  CLK, RESET, LOAD : in std_logic;
  DATA : in  unsigned(WIDTH-1 downto 0);  
  Q    : out unsigned(WIDTH-1 downto 0));
end entity counter_example;
 
architecture counter_example_a of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
  process(RESET, CLK)
  begin
    if RESET = '1' then
      cnt <= (others => '0');
    elsif rising_edge(CLK) then
      if LOAD = '1' then
        cnt <= DATA;
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;
 
  Q <= cnt;
 
end architecture counter_example_a;

More complex counters may add if/then/else statements within the rising_edge(CLK) elsif to add other functions, such as count enables, stopping or rolling over at some count value, generating output signals like terminal count signals, etc. Care must be taken with the ordering and nesting of such controls if used together, in order to produce the desired priorities and minimize the number of logic levels needed.

Simulation-only constructs

A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging. For example, the following code will generate a clock with the frequency of 50 MHz. It can, for example, be used to drive a clock input in a design during simulation. It is, however, a simulation-only construct and cannot be implemented in hardware.

process
begin
  CLK <= '1'; wait for 10 ns;
  CLK <= '0'; wait for 10 ns;
end process;

The simulation-only constructs can be used to build complex waveforms in very short time. Such waveform can be used, for example, as test vectors for a complex design or as a prototype of some synthesizable logic that will be implemented in future.

process
begin
  wait until START = '1'; -- wait until START is high
 
  for i in 1 to 10 loop -- then wait for a few clock periods...
    wait until rising_edge(CLK);
  end loop;
 
  for i in 1 to 10 loop 	-- write numbers 1 to 10 to DATA, 1 every cycle
    DATA <= to_unsigned(i, 8);
    wait until rising_edge(CLK);
  end loop;
 
  -- wait until the output changes
  wait on RESULT;
 
  -- now raise ACK for clock period
  ACK <= '1';
  wait until rising_edge(CLK);
  ACK <= '0';
 
 
  -- and so on...
end process;

See also

Notes

  1. The Seduction license is a crippleware license, placing limits on the number of language elements and nets in a design. Limits include: 25 SPICE nets, 50 Verilog signals, 15 VHDL processes, 15 Verilog processes. See What is SMASH™ Seduction? from Dolphin Integration website for details.
  2. performance beyond a few hundred lines of VHDL code decreases exponentially. See [1] for details.

External links

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